1. Field of the Invention
The present invention relates to a thin film transistor array panel for a liquid crystal display.
2. Description of the Related Art
A liquid crystal display (xe2x80x9cLCDxe2x80x9d) is one of the most commonly used flat panel displays. The LCD, which includes two panels having a plurality of electrodes thereon and a liquid crystal layer interposed therebetween, controls the transmittance of incident light by applying voltages to the electrodes to rearrange liquid crystal molecules of the liquid crystal layer.
Among these LCDs, a LCD having electrodes provided both on respective panels and a plurality of thin film transistors (xe2x80x9cTFTsxe2x80x9d) for switching the, voltages applied to the electrodes are typically used. The LCD has a plurality of pixel electrodes receiving image signals depending on the switching of the TFTs. In addition, the LCD has a plurality of gate lines respectively connected to output terminals of gate driving integrated circuits (xe2x80x9cICsxe2x80x9d) for supplying scanning signals to turn on and off the TFTs and a plurality of data lines respectively connected to output terminals of data driving ICs for supplying image signals.
The higher resolution of a LCD requires more gate lines and data lines and thus more driving ICs, thereby increasing manufacturing costs.
A thin film transistor panel is provided, which includes: a plurality of pairs of gate lines extending substantially in a horizontal direction and transmitting scanning signals, each pair of gate lines including a first gate line and a second gate line; a plurality of data lines transmitting images signals and extending substantially in a vertical direction; a plurality of pairs of thin film transistors, each transistor having a gate electrode, a source electrode and a drain electrode, each pair of thin film transistors corresponding to one pair of gate lines and one of the plurality of data lines and including a first thin film transistor and a second thin film transistor respectively connected to the first and the second gate lines of the corresponding pair of pixel electrodes and connected to the corresponding data line; and a plurality of pairs of pixel electrodes arranged in a matrix with a plurality of rows and a plurality of columns, each pair of pixel electrodes corresponding to one pair of thin film transistors and including a first pixel electrode and a second pixel electrode adjacent to each other and respectively connected to the first and the second thin film transistors of the corresponding pair of thin film transistors, the plurality of data lines arranged such that each of the plurality of data lines is located between adjacent two columns and assigned every two columns.
According to an embodiment of the present invention, the thin film transistor array panel further includes a plurality of subsidiary signal lines extending substantially in the vertical direction, and the plurality of data lines and the plurality of subsidiary signal lines are alternately arranged between adjacent two columns and overlap the plurality of pixel electrodes at least in part.
According to an embodiment of the present invention, the thin film transistor array panel further includes a storage wire overlapping the plurality of pixel electrodes to form storage capacitors. The storage wire includes a plurality of storage electrode lines extending substantially in the horizontal direction and a plurality of storage electrodes connected to the plurality of storage electrodes, each storage electrode overlapping the drain electrode. The plurality of storage electrodes extend substantially in the vertical direction, are arranged between the plurality of pixel electrodes and overlap an edge of the plurality of pixel electrodes at least in part.
According to an embodiment of the present invention, the thin film transistor array panel further includes a passivation layer interposed between the plurality of pixel electrodes and the drain electrodes and having a plurality of contacts for connecting the plurality of pixel electrodes to the drain electrodes. Preferably, the passivation layer has an uneven surface and includes a photoresistive organic material.
According to an embodiment of the present invention, the first and the second gate lines of each pair of gate lines are located at top and bottom of the corresponding pair of pixels. Each data line is arranged between the first and the second pixel electrodes of the corresponding pair of the pixel electrodes.
According to another embodiment of the present invention, each of the plurality of data lines has a dual-lined structure including a first signal line, a second signal line and a connection interconnecting the first and the second signal lines.
According to another embodiment of the present invention, the first and the second thin film transistor have rotational symmetry to each other.
According to an embodiment of the present invention, the plurality of pixel electrodes include Al, Al alloy, Ag or Ag alloy. Each pixel electrode includes a transparent conductive layer comprising ITO or IZO and an opaque conductive layer and the opaque conductive layer has an aperture portion exposing 20-30 percent of the area of the opaque conductive layer.
A method of manufacturing a thin film transistor panel is provided, which includes: forming a gate wire including first and second gate lines and first and second gate electrodes connected to the first and the second gate lines, respectively; forming a gate insulating layer covering the gate wire; forming a semiconductor layer on the gate insulating layer; forming a data wire on the semiconductor layer, the data wire including first and second data lines, first and second source electrodes connected to the first and the second data line, first and second drain electrodes respectively separated from the first and second source electrodes and data connectors connecting the first and second data lines; forming a passivation layer having an uneven surface and first and second contact holes exposing the first and the second drain electrodes respectively; and forming first and second pixel electrodes respectively connected to the first and the second drain electrodes through the first and the second contact holes, wherein a mask for forming at least one of the gate wire, the data wire, the semiconductor layer, the passivation layer and the pixel electrodes used in a first area is used in a second area by rotating 180 degrees.
According to an embodiment of the present invention, the mask comprises a plurality of opaque portions and a plurality of transparent portions. The plurality of transparent portions include a first portion with a first width, a second portion with a second width smaller than the first width, and a third portion with a third width lager than the second width and smaller than the first width, and the first portion corresponds to the first and second contact holes, the second portion to the data wire and the third portion to the remaining portions.